FIG. 1 schematically shows a cross-section view of a typical LDMOS. At high voltage applications, when the drain-source voltage exceeds the avalanche breakdown voltage of the device, electron-hole pairs are typically nucleated in the area of high electric field impact ionization under the gate termination in the drift region at the silicon surface. Electrons go to the highest potential, out the N+ drain contact; holes go to the lowest potential, out the P+ body contact, as shown (avalanche hole path 11; avalanche electron path 12) in FIG. 1.
Additionally, at zero and low gate to source bias, some of the avalanche generated hot holes will be injected into the gate oxide and/or spacer regions near the surface peak electric field point; some of which may become trapped resulting in a local reduction of the surface peak field and increase of the breakdown voltage; this phenomenon is well known as walk-out.
Besides increasing the breakdown voltage, the change in the surface potential associated with walk-out is typically also associated with other device performance changes including change in the on-state resistance. Such changes (e.g. the change in the on-state resistance) in device performance dependent on the device operation beyond breakdown are generally undesirable for practical usage.